Motor Control from Model to Hardware

2. Modelling and identification

2.1 Identifying the DC motor (Rig A)

Step responses at 7, 12 and 18 V and sine inputs at 0.5 rad/s were fitted to the DC-motor model. The fit gave $J=2.6\cdot10^{-5}$ kg·m² and $d_m=2.15\cdot10^{-5}$ N·m·s/rad, and adding Coulomb friction $F_c=1.35\cdot10^{-3}$ N·m removed the steady-state mismatch at low voltage. The electrical time constant (0.1 ms) is far below everything else, so the voltage-to-speed plant is

and the voltage-to-position plant is $23.94/(s^2+2.495s)$. Every controller in section 5 is designed on these two transfer functions.

2.2 Verifying the brushless motor model (application model)

The tool’s Faulhaber 3268 BX4 brushless motor was modelled as a DC-equivalent machine and checked against its datasheet before any controller was designed:

2.3 Drive train with gearbox and joint

The drive-train model has four states (motor and nut angles and speeds), coupled by the gearbox stiffness (739 N·m/rad) and damping. A 1 V step gives 19.56 rad/s at the motor and 0.2415 rad/s at the nut. The gearbox mode turns out to be very stiff and overdamped, so for control the drive train behaves almost as one rigid inertia.

Two unit errors found by re-running the model.

1. statespace_screw.m uses Kt (gearbox stiffness, 739 N·m/rad) in the input matrix where the torque constant kt (0.0435 N·m/A) belongs, which makes the actuator gain about 17 000 times too large.
2. The same file uses kj (axial bolt stiffness, 7.7·10⁷ N/m) where the rotational stiffness krs (3.04 N·m/rad) belongs.

Both errors appear immediately in a unit check. Lesson: check the units of every matrix entry before trusting a simulation.

3. Power stage

3.1 PWM generation on the STM32

At 40 MHz, TIM3 with ARR = 2000 produces 19.99 kHz PWM on PB4 (clockwise) and PA7 (counter-clockwise) with 2001 duty steps. That is about 11 bits, or 6 mV per step on a 12 V bridge. The motor command convention is ±2·10⁹ ↔ ±100 % duty:

/* Drive the motor in both directions: +/-2e9 <=> +/-100 % duty */
void Peripheral_PWM_ActuateMotor(int32_t con)
{
    con = con/1000000;                    /* -> +/-2000 compare counts (ARR = 2000) */
    if (con > 2000)  {con = 2000;}
    if (con < -2000) {con = -2000;}
    if (con > 0) { TIM3->CCR1 = con; TIM3->CCR2 = 0; }      /* CW  */
    if (con < 0) { TIM3->CCR1 = 0;   TIM3->CCR2 = -con; }   /* CCW */
}

PWM against the winding. The coreless motor’s electrical corner, $R/(2\pi L)=2.6$ kHz, is only 7.7 times below the PWM frequency. At stall and 50 % duty that leaves 0.71 A of current ripple, on a motor rated 0.48 A continuous.

The missing zero. The specification required “motor stationary if value is 0”. With con == 0 neither branch runs, so the previous duty stays applied. The distributed version’s failure path writes TIM3->CCR1 = 0; TIM3->CCR2 = 0; directly, next to a commented-out Peripheral_PWM_ActuateMotor(0), which is consistent with this having been discovered in testing.

3.2 Supply board (24 V → 12 V / 5 V)

Review notes (as drawn).

• The catch diode is a standard-recovery 1N4004, but a 52 kHz buck regulator needs a Schottky diode (e.g. 1N5822).
• The LM317 divider draws 1.25 mA, below the regulator’s 3.5-10 mA minimum load. Datasheet designs use $R_1$ = 120-240 Ω.
• The inductor value is not recorded in the file.

3.3 H-bridge board (A4973) and solenoid driver

Function and tests.

• Control pins: PHASE selects the direction, ENABLE switches the outputs, MODE selects slow or fast decay, and BRAKE shorts the motor through both low sides.
• Current limit: the internal chopper limits the current to $I_{\text{trip}}=V_{\text{REF}}/(2R_S)\approx1.03$ A with 3.3 V logic, meeting the < 1.2 A requirement.
• Bridge test: a 20 kHz PWM on PHASE drove one motor while a second motor, loaded by a power resistor, acted as a generator. The motor current was read across $R_S$ at 25 % and 75 % duty and at 1 kHz.
• Solenoid driver: a separate stage drove a 40 mH, 13 Ω solenoid with an IRFB7446 MOSFET, at 20 Hz and 20 kHz PWM, with and without a freewheel diode.

Review notes (as drawn).

1. The RC pin connects to a 47 µF tantalum instead of the datasheet’s ~680 pF. That gives $t_{\text{off}}\approx1.55$ s instead of about 20 µs, so every current-limit trip would switch the bridge off for 1.5 s.
2. With 5 V logic, $V_{\text{REF}}=1.56$ V exceeds the 0-1 V reference range.
3. There is no ceramic decoupling at the supply pins, and the only bulk capacitor (47 µF) sits at the datasheet’s minimum recommendation (> 47 µF, close to the device).
4. The datasheet’s block diagram has two LOAD SUPPLY (VBB) terminals, pins 9 and 16; as drawn only pin 16 is connected, so all bridge current enters through one pin. Connect both.
5. A DAC on REF would turn the chopper into a programmable hardware current controller.

4. Sensing and the signal chain

4.1 Encoder interface and speed estimate

On Rig B, TIM1 counts the encoder’s A/B edges in hardware (×4 quadrature) into a 16-bit counter that the control loop simply reads (return TIM1->CNT;). Speed comes from the difference of two readings over the control period (the M-method):

int16_t rad = encoder - oldencoder;          /* signed 16-bit difference: wrap-safe */
vel_cal = -rad*60/dt*1000/2048;              /* rpm, 2048 counts/rev assumed        */

At 2000 rpm and 50 ms about 3413 counts pass, and one count is worth 0.59 rpm. At a 1 kHz loop rate one count would be 29.3 rpm, too coarse for a speed loop. The 2048 counts/rev constant is not documented anywhere; a wrong value would be a silent gain error on speed. Rig A used plsPerRev = 3600 at 2 ms, which gives 0.87 rad/s per count.

Simulated improvement. A Kalman filter that fuses the counts with the motor current and model removes the quantization without filter lag, and it estimates the load torque. Here it is compared with the alternatives on the Rig B motor model:

4.2 Anti-alias filters and sampling

A separate board set built filters for a microcontroller ADC designed for $f_s=8$ kHz. Test signals at $f_c/3$, $f_c$ and $3f_c$ were sampled on an mbed LPC11U24 and streamed to MATLAB, and digital 200 Hz low-pass and 600 Hz high-pass filters were implemented.

Three sampling frequencies. The filter specification uses 8 kHz, the sampling program 20 kHz (one byte per sample at 921 600 baud) and the MATLAB plotter 80 kHz. Used together unchanged, every plotted frequency reads four times too high. Lesson: define $f_s$ once and store it with the data.

4.3 Current sensor board

Signal chain.

1. A 0.1 Ω shunt in series with the motor.
2. An RC input filter: series resistors, 1 nF common-mode and 10 nF differential capacitors.
3. An INA126 instrumentation amplifier with $G=5+80\ \text{k}\Omega/5.6\ \text{k}\Omega=19.3$ (roughly 45 kHz bandwidth at this gain).
4. An LM358 stage with gain ×10.

Tests. The sensor was calibrated against known currents, its output was recorded with the motor on DC and on PWM, and the signal-to-noise ratio was measured before and after low-pass filtering.

Review notes (as drawn).

• At 19.3 V/A the output saturates near ±0.55 A, and a 0-3.3 V ADC sees only 0-0.17 A.
• The REF pin is grounded, so negative currents are lost.
• Designing backwards from the ADC gives about 1.1 V/A around a buffered, ratiometric 1.65 V.
• In-line placement exposes the amplifier to the full PWM common-mode swing. Low-side placement or a PWM-rejecting current-sense amplifier avoids that.

PWM ripple and the sampling instant. Whichever sensor is used, the current must be sampled synchronously with the PWM, at the point where the ripple crosses its average:

5. Control design and results on hardware (Rig A)

5.1 Speed control

Design. The PI was designed by pole placement for no overshoot ($\zeta=0.946$) and 0.2 s settling ($\omega_0=24.3$ rad/s), giving $K_p=1.82$ and $K_i=24.7$. It was implemented as a two-degree-of-freedom controller with the reference entering only through the integrator, so a step does not kick the proportional term. Discretized with Tustin at $T_s=2$ ms:

Measured.

• A 50 rad/s step settled without overshoot, within the 1 rad/s error requirement.
• A reference of $50\sin(2\pi\cdot0.2t)$ was tracked.
• Stopping the motor by hand under the sine drove the voltage to the ±24 V rails, alternating at the reference frequency.

5.2 Position control

Design. A polynomial (RST) controller placed the dominant poles at 12 rad/s ($\zeta=1$) and the observer poles at 30 rad/s ($\zeta=0.8$):

Measured.

5.3 Servo control

A trapezoidal trajectory planner (500 rad/s², 210 rad/s, chosen from the identified model so that the voltage never saturates) and a model-following feedforward made 10 rad and 100 rad moves with about 0.5 s rise time. The real motor tracked as well as the simulation.

5.4 Sampling, delay and saturation (re-simulated)

5.5 Robustness

The sensitivity $S$ and complementary sensitivity $T$ were compared for different observer polynomials. The same method was applied to a velocity controller for a valve-controlled hydraulic cylinder, tested against an external force, a change of load mass and sensor noise.

6. Embedded implementation (Rig B)

6.1 Firmware architecture

The firmware has four modules with fixed header files (core, peripherals, controller, application), written as if by four teams in parallel. The same PI law was run in three execution models:

1. Super-loop. The loop polls HAL_GetTick() and runs the controller when millisec % PERIOD_CTRL == 0; the reference toggles between ±2000 rpm every 4 s. The PI is an incremental Tustin form that receives the elapsed time, so it works at both 10 and 50 ms.
2. RTOS. Keil RTX (CMSIS-RTOS v1) virtual timers (50 ms and 4 s) signal a control thread and a reference thread. The HAL’s SysTick, SVC and PendSV handlers had to be removed to avoid clashing with the kernel’s.
3. Distributed over TCP. A client board samples the encoder and drives the motor; a server board computes the PI. Each period the client sends the speed (4 bytes, SF_TCP_NODELAY), waits in a blocking recv() and actuates; on failure it zeroes the PWM.

6.2 Re-executing the firmware

controller.c and peripherals.c were replayed in Python with exact C integer semantics (32-bit wrap, truncating division, the original signed/unsigned conversions) against a model of the motor. The replay assumes a 12 V supply, sign-magnitude drive, 2048 counts/rev and rotor inertia only.

Two overflow mechanisms.

• RTOS version. ki*I exceeds 32 bits before the clamp, and the back-calculation term (u - v)*kant is $9\cdot10^5$ times stronger than a deadbeat correction, so it overflows too.
• Final version. The clamp at $\pm2\cdot10^9$ comes after the addition, leaving only $1.47\cdot10^8$ of headroom. With the rotor held at 50 ms one increment is $1.56\cdot10^8$: the sum wraps and the clamp turns it into full reverse duty. At 10 ms the increment fits.

6.3 Code review findings

6.4 From control equation to torque

At the steady state of a +2000 rpm reference:

1. Sensor. Every 50 ms the thread reads TIM1->CNT; about 3413 counts have passed.
2. Estimate. velocity ≈ 2000 rpm.
3. Control. The PI holds pidout ≈ 4.1·10⁸ (20.6 % of 2·10⁹).
4. PWM. TIM3->CCR1 = 412, so PB4 is high for 10.3 µs of every 50 µs.
5. Bridge. The shield applies 12 V for 20.6 % of each period, 2.47 V on average.
6. Winding. (2.47 − 2.38 V back-EMF) / 3.42 Ω ≈ 25 mA, the no-load current, with about 0.5 A of PWM ripple.
7. Torque. $k_ti$ ≈ 0.29 mN·m balances friction, and the speed holds.

7. Application study: a bolt-tightening drive (simulation)

The loop was then scaled to an application: the drive of an Atlas Copco Tensor ETV STB62-50-B10 nutrunner, with a Faulhaber BX4 brushless motor, a 9 × 9 planetary gearbox and an M8 bolted joint. The target is 25 N·m, finishing at 3 rad/s at the nut.

Gear ratio. The requirement is a constant-power curve at the motor (about 83 W), close to the motor’s 99 W peak at 24 V.

• With $n=81$ the clamp point (0.34 N·m, 243 rad/s) needs 22 V and 7.9 A, but the free speed is only about 59 rpm against the product’s 375 r/min.
• Reaching 375 r/min needs $n\le18.3$, and then the clamp needs 1.52 N·m, twice the stall torque.

The specified motor cannot meet both requirements.

Joint model. Without friction the model predicts 2.82 GPa bolt stress, far above the 640 MPa yield. With thread and under-head friction ($\mu=0.2$), 25 N·m gives 11.7 kN of preload and 321 MPa, reached about 44° after snug.

Stopping at the target. If the drive keeps commanding the clamp torque and lets the joint stop the rotor, the rotor’s 0.18 J of kinetic energy winds the joint a further 0.11 rad: 3.5 N·m (14 %) overshoot. Cutting the current exactly at the target gives about 0.2 N·m, but then every millisecond of torque-measurement delay adds 0.1 N·m. Slowing to 0.5 rad/s before the target brings the torque-limited overshoot down to 0.6 N·m, which is why production tools tighten in two steps.

Energy. After the unit errors of section 2.3 are fixed, the clamp phase alone needs about 20 J: 7.7 J of copper loss, 10.7 J of mechanical work and about 1 J of no-load losses. The original model gave 140 J per tightening and about 2000 bolts per 2.6 Ah charge.

8. Brushless drive shields for the BX4 (design)

The application study showed what a real tool drive needs: a three-phase bridge for the BX4, about 8 A at the clamp point, current measurement and a speed estimate that works at low speed. Both rigs in this project drive brushed motors through H-bridges, so the next hardware step is a pair of Nucleo-L476RG shields for the BX4. Both are built around the same power stage:

• a TI DRV8323S gate driver (6-60 V, SPI-configured, three integrated current-sense amplifiers);
• six Infineon BSC028N06NS 60 V MOSFETs (2.8 mΩ);
• a 24 V input with an SMBJ33A TVS, bulk capacitors and decoupling on each bridge leg.

They differ in how the motor is commutated and in what is measured. That makes them the hardware versions of the velocity loop and the torque loop in the theory post (Parts E, G and I).

8.1 Velocity shield: six-step with Hall commutation

Design notes.

• Speed from Hall edges. The speed comes from timing the Hall edges (the T-method of Part E.5): $\hat\omega_e=(\pi/3)/\Delta t_{\text{edge}}$. With two pole pairs that is 12 edges per mechanical revolution. At the clamp speed (243 rad/s) an edge arrives every 2.15 ms, so a 1 MHz capture clock resolves 0.05 %. The estimate is fresh only once per edge, about 465 times a second at clamp speed and much less near standstill, where a timeout must declare zero speed. A 1 kHz speed loop therefore sees a sampling rate that changes with speed.
• DC-link current. The DC-link shunt carries the conducting phase current only during the PWM on-time. The current-limit sample belongs in the middle of the on-time, triggered by the PWM timer.

8.2 Torque shield: FOC with three-shunt sensing

Design notes.

• Current range. The DRV8323S amplifiers are bidirectional around $V_{\text{REF}}/2$, with gains of 5, 10, 20 or 40 V/V. With 5 mΩ and a gain of 20, a 3.3 V ADC covers ±16.5 A at 8 mA per LSB. That is two times headroom over the 7.9 A clamp current, and the design follows the “backwards from the ADC” rule (Part E.4) that the old lab sensor missed.
• When to sample. Low-side shunts see a phase current only while that leg’s low-side MOSFET conducts. With centre-aligned PWM all three low sides conduct in the zero vector at the centre of the period, which is why the ADC is injected there (Part F.1).
• Losses. At 7.9 A each shunt dissipates 0.31 W and each conducting MOSFET about 0.17 W.
• Input filters. The Hall filter (1 kΩ, 1 nF, $\tau$ = 1 µs) and the encoder filter (330 Ω, 100 pF, $\tau$ = 33 ns) reject nanosecond spikes while passing edge rates of hundreds of kHz and several MHz respectively.

8.3 Open points before ordering

1. Unannotated values. The values of the CSA output filters, the bus-voltage divider and the charge-pump and decoupling capacitors are not shown on the schematics yet. Their cut-off and attenuation must be checked against the 20 kHz PWM and the ADC sampling time (Part F.3).
2. Regenerative braking. Stopping the BX4 from no-load speed on a 24 V bench supply with 470 µF of bus capacitance would push the bus to about 70 V (Part J.4 of the post), above the 60 V MOSFETs and the DRV8323S supply range. The TVS is meant for short transients, not for absorbing braking energy, so braking needs a current limit on regeneration or a brake chopper.
3. Battery voltage. The SMBJ33A’s 33 V stand-off suits a 24 V supply but is marginal for a fully charged battery pack above 33 V.
4. SPI clock and the LED. SPI1 uses D11-D13; D13 (PA5) also drives LED LD2, which will flicker with the SPI clock. That is harmless.
5. Velocity shield routing. Its PCB still needs the remaining connections routed and a design-rule check.

8.4 Reference Simulink models of both drives

Before any firmware for the shields, both drive types were simulated in Simulink with the BX4 constants of the application study, the 20 kHz control period of the STM32 firmware and the same speed loop, so they can be compared like for like. The model files are not published here; only the structure and the results are.

PMSM with field-oriented control (simulated structure). The speed PI sets $i_q^$ ($i_d^=0$). Two current PIs work in the rotating frame with the cross-coupling and back-EMF feed-forward terms $-\omega_eL_qi_q$ and $\omega_e(L_di_d+\lambda)$. The voltage vector is scaled back onto the circle $V_{dc}/\sqrt3$ (the linear SVPWM limit), delayed one sample and rotated back to the stator frame. The plant is the dq model; $i_a$ and $i_b$ are rebuilt from it and pass through Clarke and Park again, as a three-shunt measurement would.

BLDC with six-step commutation (simulated structure). The speed PI sets the bridge current reference and a current PI sets the signed duty. The rotor angle is converted to degrees and shifted, wrapped with a mod block and compared with 180° to give the three Hall bits (edges at 30° + k·60°). A Combinatorial Logic block holds the six-step truth table (Hall code in, six gate signals AH, AL, BH, BL, CH, CL out). In parallel, three lookup tables give the trapezoidal back-EMF shapes $f_a,f_b,f_c$ of the three phases, and the gate signals select the conducting pair: $s=\tfrac12\sum_x(H_x-L_x)f_x$. The plant is the lumped model of the two conducting phases: $L_{ll}\,di/dt=v-R_{ll}i-k_es\omega$ and $T_e=k_ts\,i$. In the flat part of the trapezoid $s=1$; the ramps of the shapes appear only around the commutation instants.

Simulated response. A 300 rad/s step at 10 ms and a 0.1 N·m load step at 100 ms (the plots end at 200 ms):

What these models do not contain. Both use an average-value inverter, so there is no PWM ripple, dead time, MOSFET drop or bus-voltage sag, and no sensor noise or quantisation. The rotor angle and speed are the plant states, not the Hall-edge T-method estimate of section 8.1. Friction is $b=0$, as in the project data. The PMSM flux linkage is derived from the torque constant by assuming a sinusoidal machine, which the BX4 only approximates. The BLDC model lumps the two conducting phases and ignores the freewheeling phase, so torque ripple at commutation is understated. None of this has been checked against the shields, which are not built.

9. Results and lessons

Lessons.

1. Design the sensor backwards from the ADC, and the sampling instant from the PWM.
2. Choose the sampling period from delay, not from habit. A direct discrete design survives periods that break an emulated one.
3. Every loop saturates. Anti-windup and arithmetic headroom must be tested with a stalled rotor, not only with a step.
4. Units are the cheapest test. Every serious error found here was a unit or range mismatch between two pieces written separately.
5. Re-execute old work. Re-running models and firmware against each other found more than re-reading them did.

10. Next steps

• Finish the BLDC shields. Annotate the remaining values, route the velocity shield, run design-rule checks, then order and bring up the velocity shield first (simpler firmware, Hall commutation in the driver).
• Firmware for the shields:
  • a speed PI on Hall-edge timing for the velocity shield;
  • FOC with PWM-centred ADC sampling for the torque shield;
  • the Kalman speed estimator of section 4.1 on the encoder.
• Fix the Rig B firmware: add in 64 bit before clamping, add the zero-duty branch, correct the back-calculation scaling, and test the stalled rotor on hardware.
• Port to Zephyr on the same Nucleo board.

Provenance table

Status codes: B built and tested · M measured on hardware · Mo modelled/simulated · D datasheet · R re-derived for this page · A assumed · U unknown (not in any surviving file).

Credits and sources

The work was done during my master’s at KTH:

• Rig A: workshops in MF2007 Dynamics and Motion Control, with Huanyu Chen and Jiahao Wang; course responsible Lei Feng.
• Rig B: the group project in MF2103 Embedded Systems for Mechatronics, under Jad El-khoury and Martin Törngren.
• Boards: individual labs in MF2043 Mechatronic Electronics; the sampling code and plotter were provided by the course.
• Application model: the MF2030 Mechatronics group project “An Electric Nut-Runner for Tightening of Bolted Joints”, with Gowtham Raj Rangaraju and Pak Chuen Hau.

Datasheets: Assun AM-CL1643MB-1210; Faulhaber 3268 G 024 BX4; Allegro A4973; TI LM2576, LM317, INA126; STMicroelectronics RM0351, UM1724; Atlas Copco Tensor STB product sheets.

Images: Nucleo-L476RG and W5500 shield from the Zephyr Project documentation (Apache-2.0); C2000 LaunchPad set-up by Brihaspati (CC BY-SA 4.0) via Wikimedia Commons. Diagrams and plots are my own; simulations and code replays were re-run in Python for this page.